A microprocessor used in many large computer systems may include memory elements, combinational logic, and a clocking system. The memory elements may be arranged in sets, sometimes called registers that may correspond to the word size used in a computer system. Between at least some sets of memory elements are combinational logic circuits. At the end of a clock cycle, which is also the beginning of the next clock cycle, data on the output of the combinational logic circuitry is stored in a first set of memory elements. This data appears on the output of the set of memory elements, and therefore on the input of other combinational logic circuitry. The other logic circuitry performs the designed logic function on the data, and at the end of the clock cycle the output of this combinational logic is stored in a next set of memory elements. This process is repeated as the computer operates. In other words, data is processed by combinational logic circuity, stored in memory elements, and then passed on to other combinational logic circuitry. A system clock, often a PLL (Phase Locked Loop) controls the clocking of information from one state to the next state.
On many microprocessors a high frequency clock signal is distributed across an entire die. As clock speeds exceed 2 GHz and die size exceeds 400 square millimeters, clock distribution may become more difficult. An ideal PLL aligns the phase (edge time) of a clock signal arriving at a memory element to the system clock. However, this usually does not happen in practice. Long term jitter or variation of the phase alignment increases as the size of a die increases. As a result, the time allowed to propagate data from one memory element, through combinational logic, into another memory element is reduced. This time is often called a “clock budget.”
In addition to long term jitter, a PLL may produce cycle-to-cycle jitter. Cycle-to-cycle jitter is a measure of the variation in the clock cycle due to the PLL. Cycle-to cycle jitter may occur, among other things, due to temperature variation or changes in on-chip voltages. In order to reduce the probability of system errors, the clock budget should be reduced in order to compensate for cycle-to-cycle jitter.
Measuring the jitter performance of microprocessors can be a difficult testing challenge. The cost of external equipment and testing time can be expensive. In addition, the process of probing a die in order to measure jitter usually destroys a die. Because a die is usually destroyed after one probing, additional jitter measurements at different locations on a die are usually not possible. There is a need in the art to reduce the cost of measuring jitter, reduce the number of die that are destroyed by probing, and make more than one jitter measurement on an individual die.
An embodiment of this invention allows for on-die measurement of cycle-to-cycle jitter at multiple locations through out the clock distribution. These measurements can be made without probing the die thus reducing the number of die destroyed and reducing the cost of measuring jitter.